MSc dissection in Computer Engineering Department at UOT about

"Development of FPGA-Based Multi Core System on-Chip for Big Data Application"

For student (Sarah Mahdi Karim), her thesis is about five chapter:-

• The first one is the introduction.
• The second chapter, MIPS architecture.
• The third chapter, the design of the Multicore Multicore Logic Gates Array (FPGA).
• The fourth semester, practical results.
• The fifth chapter, conclusions and future work.

This thesis aims to design a multicore processor with the ability to execute a single instruction on several data elements simultaneously (SIMD) for implementation on the FPGAs, where the proposed processor can be used for educational purposes and to produce a general purpose processor dedicated to multimedia and big data application.

This thesis discussed designing a 32-bit MIPS processor using VHDL.

 The researcher concluded that the usage of the proposed processor includes (6184 numbers of chipset register), (6788 number of LUT chips), (1160 number of LUT-FF pairs in full use), (67 number of restricted IOBs), (6 number of RAM / FIFO block For FPGAs. The total power was (3.422) watts and the hour period was equal to (7.329) nanoseconds (frequency: 136.444 MHz) for the proposed processor.

The discussion committee consisted of:

• Prof. Dr. Hassan Jalil Hasan, UOT / Computer Engineering Department / the head
• Prof. Dr. Wamid Nizar Falih UOB / College of Engineering / Computer Engineering Department / member
• Prof. Dr. Ahmed Mazhar Hassan UOT / Control and Systems Engineering Department / member.
• Prof. Dr. Ahmed Sabah Abdul Amir UOT/ Computer Engineering Department / member
• Bassam Muhammad Saeed UOT/ Computer Engineering Department / member and supervisor.